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Product No. Product Description Product Status
CS6209 Enhanced HTTP Server with 128K Flash Production
 General Description:
The CS6209 is an integrated device specifically targeted on embedded control applications which require network access. It incorporates a high-speed one-cycle 8051-compatible micro-controller core along with embedded 128K-byte program flash consist of two 64K-byte flashes which could do in system programming (ISP) and in application programming (IAP), 32K bytes data SRAM. CS6209 includes an on-chip 32K bytes BOOTROM which support update embedded flash or external flash by UART or Network. External system memory is easily added to CS6209, with up to 256K bytes of code memory and 160K bytes data memory facilitating large programs.

Network access is provided by moving packets by the Media Access Control (MAC) block. There are shared 32K byte packet buffers local to the MAC. An on-chip 10BASE-T/100BASE-TX Ethernet transceiver allows direct connection to a twisted-pair network environment. Meanwhile, CS6209 supplies standard MII interface by multiplex with GPIO.

The CS6209 also includes standard general purpose I/O port1 and port3. Two full-duplex serial port(UART), multiple interrupt source with two level priority, and 3 16-bit timer are shared with these ports. Additional two 8-bit wide programmable I/O are also included for external control and multiplexed with either MII interface or PCMCIA interface. Two programmable master/slave I2C interfaces are also included for communications with other hosts or slave devices such as EEPROM. A 12-Bit SAR analog-to-digital converter allows the CS6209 to directly interface with audio inputs to facilitate audio designs.

The CS6209 has built-in simple real-time clock to keep track of time stamp of seconds, minutes and hours. It operates on the low-frequency 32.768KHz reference clock crystal.
 Features:
•  CPU
•  One-cycle 80C32 instruction set compatible core
•  Operate on 50MHz clock rate
•  On-chip 128K-byte program flash
•  On-chip 256 bytes of internal data SRAM
•  On-chip 32K bytes xdata SRAM shared with MAC
•  Non-multiplexed external program and data memory interface
•  Programmer model is 8051 compatible
•  Ethernet
•  Support both 10Mbps and 100Mbps data rate
•  Support both full-duplex and half-duplex operation
•  Integrated Ethernet 10/100 PHY Compliant with IEEE 802.3/802.3u 100BASE-TX specification
•  Support Xon/Xoff full duplex flow control method
•  Hardware checksum capability to speeds network protocol processing
•  On-chip 32K bytes receive and transmit buffer shared with CPU
•  Standard MII interface multiplexed with GPIO Integrated System Resources
•  Integrated system resources
•  Peripheral
•  One watch dog timers
•  Three 16-bit timers
•  Up to 32 general purpose I/O
•  Two I2C Interface both programmable for master or slave operation
•  Two full-duplex UART
•  12-bit ADC
•  8-bit PCMCIA interface
•  Two channel 8-bit PWM
•  Real Time Clock
•  On-Chip Flash Programming
•  I2C mode ISP
•  Ethernet ISP using TFTP by BOOTROM
•  UART ISP by BOOTROM
•  In Application Programming by user software
•  Hardware code protect for embedded flash
•  Firmware
•  On chip HTTPD server
•  TCP/IP network stack accessible by application
•  ARP, IP, ICMP, UDP, TCP, DHCP etc.
•  Others
•  Wide range of voltage operation from 3.0 to 3.6V
•  3.3/5 V tolerant I/O
•  128 pin PQFP

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