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Single Cycle 8051 CPU core, maximum operating clock up to 20 MHz |
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Single + 5V (CS8959) power supply |
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Embedded 171K-byte Flash ROM with ECC |
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4352-byte RAM with ECC
-256-byte Internal RAM
-4K-byte Auxiliary RAM
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9 channels general PWM outputs
-7 channel of 8-bit supporting Programmable PWM output frequency
-2 channel of 8-bit supporting Programmable PWM output frequency with 4-bits flexible time base period
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Maximum 75 I/O pins |
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ECC generation with 1-bit correction |
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Three 16-bit Counters/Timers |
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One programmable buffered clock output ports to drive peripheral devices |
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Built-in one Master and two Slave I²C ports |
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Built-in SPI controller |
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Maximum 13-channel 12-bit A/D converters with Flag indication
-Conversion time: 12.5 ms
-Input voltage level: 0 ~ +VDD
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Hardware ISP (In-System-Programming), no Boot Code required |
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Two Full-duplex UARTS |
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Two CAN controllers with gateway function. Specification Version 2.0 Part A and B, each one CAN controller provides
-Bit rate up to 1Mbit/s
-32 Message Objects
-Each Message Object has its own Identifier Mask
-256 Bytes FIFO
-Interrupt can be masked
-Dispatching registers
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Multi interrupt sources |
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Programmable Watch Dog Timer |
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Built-in Real Time Clock (RTC) |
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Dual Data Pointer (DPTR) |
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Flash-ROM program code protection |
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JTAG interface Debug System |
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Single +5V supply voltage |
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Industrial operating temperature range (-40¢XC ~ +85¢XC) |
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100-pin QFP package with RoHs compliance |
