| • |
8051 core, 12MHz operating frequency with double CPU clock option
|
| • |
0.35um process; 5V/3.3V power supply and I/O; 3.3V core operating |
| • |
1024-byte RAM; 64K-byte program Flash-ROM support In System Programming (ISP) |
| • |
Maximum 14 channels of PWM DAC
|
| • |
Maximum 31 I/O pins
|
| • |
SYNC processor for composite separation/insertion, H/V polarity/frequency check, polarity adjustment and programmable clamp pulse output
|
| • |
Built-in self-test pattern generator with four free-running timings
|
| • |
Built-in low power reset circuit |
| • |
Compliant with VESA DDC1/2B/2Bi/2B+ standard
|
| • |
Dual slave IIC addresses; H/W auto transfer DDC1/DDC2x data
|
| • |
Single master IIC interface for internal device communication |
| • |
4-channel 6-bit ADC |
| • |
Watchdog timer with programmable intervals
|
| • |
Flash-ROM program code protection selection
|
| • |
40-pin DIP, 42-pin SDIP or 44-pin PLCC package |
| • |
Green products like Pb-Free Packages or all Green Packages available |
